Forum Discussion
Altera_Forum
Honored Contributor
13 years agoThanks all.
Yes, my 32-bits flash is made up of 2 16-bits single flash. The data lines are from d[0] - d[15] for 1st flash and d[16] - d[31] for 2nd flash. I've ensured that add[2] is connected to the FIRST address pin on flash memory chip. "you need to take special care during any write/erase operations to ensure that not only are both devices given the requests, but that the driver actually waits for both parts to finish" Is Altera CFI software driver able to do this? Which Stratix V FPGA devkit did you mean? As far as I'm concerned, Altera.com has the latest SV devkit which is 100g development kit, stratix v gx edition (http://www.altera.com/products/devkits/altera/kit-stratix-v-gx-100g.html). This devkit only has 1 CFI flash. Did you mean that as of now, Altera nios tools couldn't support 16bits x 2 CFI? Thanks.