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Altera_Forum's avatar
Altera_Forum
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20 years ago

Block Cipher Hardware Design

Hi all,

I'm design a block cipher and will integrate it with Nios II.

1. What method is the most flexible and easier. (a) design coprocessor for the Nios II using custom instruction or (http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/cool.gif develop a new component for SOPC builder.

2. If use method (http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/cool.gif how about HAL (software development)

3. How to utilised all 128 bit avalon slave bus for writedata and readdata? used it direct connect like PWM example. How about HAL?

Thanks.

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    20 years ago

    Hi,

    I would add it as a component and not as a custom instruction, presuming your block cipher hardware will take up more than a few clock cycles to iterate.

    Adding it as a custom instruction would stall the processor until the block cipher hardware is done.

    Whereas, if you add it as a component, you can still have your processor send data to the block cipher hardware to proccess, go off and do something else, and get interrupted when the block cipher is done.

    http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/wink.gif

    On the HAL, you can write directly to the component base address (which presumably is your writedata port) or make some makros for it. I would not go further as to develop a whole HAL unless you have multi proccesses in your block cipher hardware to control. In essence, the Nios should only see the block cipher hardware as In and Out ports, with maybe an interrupt signal. The Nios should Not need to know what goes within the block cipher hardware.