Block Cipher Hardware Design

Hi,

I would add it as a component and not as a custom instruction, presuming your block cipher hardware will take up more than a few clock cycles to iterate.

Adding it as a custom instruction would stall the processor until the block cipher hardware is done.

Whereas, if you add it as a component, you can still have your processor send data to the block cipher hardware to proccess, go off and do something else, and get interrupted when the block cipher is done.

http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/wink.gif

On the HAL, you can write directly to the component base address (which presumably is your writedata port) or make some makros for it. I would not go further as to develop a whole HAL unless you have multi proccesses in your block cipher hardware to control. In essence, the Nios should only see the block cipher hardware as In and Out ports, with maybe an interrupt signal. The Nios should Not need to know what goes within the block cipher hardware.