Basics of „Timing Constraints“

I think this has the info

http://altera.com/literature/hb/qts/qts_qii52005.pdf (http://altera.com/literature/hb/qts/qts_qii52005.pdf)

regards

pavan

Hello pavan,

Thank you for your response and the interesting link. Unfortunately the document describes the steps to optimize the timing. At the moment I don’t know if I should optimize anything because I didn’t setup any timing constraints, except the main system clock. And because of that the timing results are OK due to the fact that the one any only timing constraint (system clock) could be met.

Here is an example of my problem in understanding timing constraints. The example is based on the serial DAC Ad5545 from Analog Devices. The device has four inputs: SDI, CLK, CS# and LDAC#. The signals are connected to the FPGA directly. The datasheets is giving some more information about the interface timing:

CS# to Clock Setup (tCSS): 0 ns

Clock to CS# Hold (tCSH): 10 ns;

Data Setup (tDS): 5 ns

Data Hold (tDH): 10 ns

I know the meaning of the given timing information but I don’t know how to transfer this information into timing constraints.

Regards,

niosIIuser

Hello,

Does none of you have more information about this topic? That’s curious because designing timing constraints should be the normal work.

Anyone? Anything?

Regards,

niosIIuser

online video tutorial material provided for TimeQuest Timing Analyzer training available for free is quite useful

Rgds

Silva

Tons of information here, from online tutorials and quick start guides to full documentation.

http://www.altera.com/support/software/timequest/sof-qts-timequest.html