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Manprocoder's avatar
Manprocoder
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1 year ago

AXI4 DMA Master Error

Hi expert, I am building SoC system that includes components as follows: + CPU + onchip_memory_2_0 + onchip_memory_2_1 (source address) + onchip_memory_2_2 (destination address) + IP (Active As...
Nios Cpu
SueC_Altera's avatar
SueC_Altera
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1 year ago

Hi Manprocoder,

I've asked our engineering team to look at this issue. We tried running your design in simulation and it got hung with no awvalid or arvalid asserted. They then created a separate design that uses the AXI4 1x1 bridge with Interconnect (Data width: 32b to 64b) and HDL generated in Quartus18.1std. Everything worked fine in this design.

I'm asking to see if we can share this design with you.

Sue

Manprocoder's avatar
Manprocoder
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1 year ago
Hi @SueC_Altera,
Sure. I have a strong desire to view your design for reference.