Avalon tristate slave timing control

Hi,

I am designing an interface to byte wide Nand Flash using the avalon tristate slave interface. One issue I have run into is that the flash comes up in a slow interface timing mode until it is written with an updated timing mode command. I am using fixed wait and hold state timing on the avalon bus, but from what I can tell the Nios cannot change this timing as it was set in SOPC builder. I would like to run the interface at the higher speed once the flash is set to the new timing mode, but I need to first access it at a slower speed to change the timing mode.

Is there any way for the Nios to control the wait/hold state settings for the avalon bus? Alternatively, could I use a divided down version of the clock and a clock mux to select a slower interface speed during initialization of the flash, or will this cause other problems?

One other related item: since the tristate slave interface is 8 bits and the bus master is 32 bits, when the Nios reads the flash it always does 4 byte reads to generate a 32 bit word, even if it is only trying to read a byte. Most read operations are on a 32 bit word basis, so I like the performance improvement this gives, but there are a few cases where I would like to do a single byte read. Since the Nand flash is a sequential (streamed) interface, the extra 3 byte read cycles when reading a byte are a problem. Is there any way to force the avalon interface to only generate a single byte read cycle to the flash?