Avalon tristate slave timing control

If your interface generates the 'busy' signal itself, then the timings can be controlled by your logic - so can be changed once the fast mode is enabled.

If you only need writes at the slow speed, perhaps it is possible to leave the avalon MM interface running at full speed, and ensure the software doesn't do the cycles too close together.

It is the Nios cpu that always does 32bit reads (rather than specify the individual byte enables). I suspect that the only way to do a single byte transfer is to double map the flash - returning a byte in the low bits at the alternate address.