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Altera_Forum's avatar
Altera_Forum
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20 years ago

Avalon Master with 8Bit Transfers

Currently i am trying to port my sopc module from being a pure avalon slave into a combination of a avalon slave that will hold only some control and status registers and an avalon read and an avalon write master.

The idea behind that is that my modules can directly store data into sdram or read from sdram. this will save a lot of m4k memory for signaltap :-)

Implementing a pure avalon slave is easy.

Implementing an avalon master following the avalon bus specification seems to be easy to but i still have some questions. maybe somebody here can help me to save time ...

One point is that both avalon master will read or write 8Bit.

i have setup for both avalon master :

- clk

- address

- waitrequest

and read / readdata resp. write / writedata

do i need to set the byteenable signals too?

as readdata and writedata are both 8 bit wide ?

or does the avalon do the job using a0 and a1 to create the byteenables ?

what if the sdram is 16bit and not 32bit ?

what is also not clear to me is what if one of my masters is accessing a slave that is currently accessed by another master ? this will happen if i try to access the sdram. will i receive waitrequest ?

Are there any examples out there how to implement a master ?

Regards.

Michael Schmitt

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    20 years ago

    Hi MSchmitt,

    I asked me the same question when I started to implement an Avalon Master port to my design.

    In fact it is very easy.

    When you read chapter 2 and 4 from Avalon Interface Specification (mnl_avalon_spec.pdf), you can see that if you made a 8 bits data width interface, you don't have to worry about byteenable lines.

    Those are managed by the Avalon Switch Fabric.

    I have made a simple Avalon Master component with only those signals 

    Entity simple_master is
  port ( gls_clk    : in  std_logic;                     -- device clock
         gls_reset  : in  std_logic;                     -- device asynchronous reset
         
         -- Avalon Master interface signals
         avm_m0_address     : out std_logic_vector(31 downto 0); 
         avm_m0_writedata   : out std_logic_vector(7 downto 0);
         avm_m0_write       : out std_logic;
         avm_m0_waitrequest : in  std_logic;
         
         -- global signals
         tx          : out std_logic;
         rx          : in  std_logic;
         oe          : out std_logic
       );
end entity;

    This component is able to transfer data received by serial link directly to RAM.

    You don't have to worry about dual access or clock domain, this is managed by the switch fabric, the only signal very important in your case is waitrequest.

    Your write (or read) signal has to be asserted until waitrequest is deasserted. This ends the transfer cylce.

    Hope this can help you

    Regards

    Fabrice Mousset
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    20 years ago

    Thanke FMousset,

    i have already implemented this 8 Bit Master but i had to implement them all as 32 bit masters, as under worst case situation there wont be enough cycles left for all masters to gain access to the sdram.

    but i agree it was very easy.

    Regards

    Michael Schmitt