Avalon Master with 8Bit Transfers

Hi MSchmitt,

I asked me the same question when I started to implement an Avalon Master port to my design.

In fact it is very easy.

When you read chapter 2 and 4 from Avalon Interface Specification (mnl_avalon_spec.pdf), you can see that if you made a 8 bits data width interface, you don't have to worry about byteenable lines.

Those are managed by the Avalon Switch Fabric.

I have made a simple Avalon Master component with only those signals

Entity simple_master is
  port ( gls_clk    : in  std_logic;                     -- device clock
         gls_reset  : in  std_logic;                     -- device asynchronous reset
         
         -- Avalon Master interface signals
         avm_m0_address     : out std_logic_vector(31 downto 0); 
         avm_m0_writedata   : out std_logic_vector(7 downto 0);
         avm_m0_write       : out std_logic;
         avm_m0_waitrequest : in  std_logic;
         
         -- global signals
         tx          : out std_logic;
         rx          : in  std_logic;
         oe          : out std_logic
       );
end entity;

This component is able to transfer data received by serial link directly to RAM.

You don't have to worry about dual access or clock domain, this is managed by the switch fabric, the only signal very important in your case is waitrequest.

Your write (or read) signal has to be asserted until waitrequest is deasserted. This ends the transfer cylce.

Hope this can help you

Regards

Fabrice Mousset