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Altera_Forum
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14 years ago

avalon fifoed uart - problem with baudrate setting

Hi, I am setting the baudrate as 115200 but the actual baudrtae looks to be 9600. any ideas? i am trying to add printf to check what is happening in altera_uart.c with pr_err in altera_uar...
Altera_Forum's avatar
Altera_Forum
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14 years ago

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I had an issue with Qsys in Quartus v11.0 generating HDL with an incorrect baud rate divisor when using the "UART (RS-232 Serial Port)" component.

This problem seems to have been fixed in v11.0 SP 1.

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Looks like that.

Either IP problem or some kind of initialization problem of the core in FPGA.