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Altera_Forum
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19 years ago

Avalon Bus not working after Upgrade

I have a custom board with a previously working NiosII inside a Stratix device. Because of some unrelated firmware upgrades I was preparing to make, I was forced to upgrade to Quartus 6 + the service pack and patch. I also went ahead and upgraded NiosII EDS to the latest version. I re-generated w/ SOPC and compiled the design w/ Quartus (no changes to any firmware or the core) and lo and behold... problems.

The core can access its internal peripherals same as before the upgrade. When trying to access external peripherals (i.e. flash, external ram) it no workie. Checking the signals on a test header shows that all the signals are there in correct sequence w/ proper setup/hold times during a write. During a read, same deal except data lines never change! The test header signals are routed directly from the FPGA.

Looks like a hardware problem w/ external peripherals but that is impossible because we can load an .sof made w/ older version of Quartus and EDS into the same board and works fine...

Sorry for the long explanation, but has anyone seen anything like this before? Or maybe have some ideas for debugging that could be useful? Altera Support seems to be at a loss right now. Thanks in advance for any comments or help!!!

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    19 years ago

    Do you have multiple clock domains?

    When I upgraded, I forgot to change the clock domains going to some components, and it had all sorts of strange behavior.

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    originally posted by sph147@Nov 7 2006, 11:55 AM

    i have a custom board with a previously working niosii inside a stratix device. because of some unrelated firmware upgrades i was preparing to make, i was forced

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    ....

    thanks in advance for any comments or help!!!

    <div align='right'><{post_snapback}> (index.php?act=findpost&pid=19272)

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  • Altera_Forum's avatar
    Altera_Forum
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    19 years ago

    Thats a good thought. There are two clock domains but the second one is not connected to the Nios or any of its peripherals. So I&#39;m shying away from the idea clock domain problems.

    --- Quote Start ---

    Do you have multiple clock domains?

    When I upgraded, I forgot to change the clock domains going to some components, and it had all sorts of strange behavior.
  • Altera_Forum's avatar
    Altera_Forum
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    19 years ago

    Update:

    By writing to certain peripherals with a "non-working" load and then reconfiguring the FPGA with a working load, I can read back the data from the peripherals. This shows me that writes are working correctly.

    Using Signal Probe and interfacing directly to the data bus from a peripheral I can see that when reads are done, the correct information is at least arriving at the pins of the FPGA. This tells me that the control signals going to the ram peripheral are working correctly.

    I don&#39;t know a whole lot about the avalon bus architecture or the "avalon_slave_arbitrator" that the data bus interfaces to so I was wondering at some other signals internal to the avalon that I could look at for proper operation? Thanks!
  • Altera_Forum's avatar
    Altera_Forum
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    19 years ago

    If you are familiar with Signal Tap or Signal Probe, you can dig into the Avalon interface for your peripheral. Assuming your peripheral uses fixed timing (no wait signal), you should find three signals of interest on the Avalon interface for probing: a chip select, a read strobe, and read data. (The chip select and read strobe may be either positive or negative polarity, but you should be able to tell by the signal name.) The read access is pretty standard: chip select asserted, read strobe asserted (can be concurrent with chip select), and the data is sampled at the end of the cycle.

    --- Quote Start ---

    originally posted by sph147@Nov 8 2006, 06:56 PM

    update:

    by writing to certain peripherals with a "non-working" load and then reconfiguring the fpga with a working load, i can read back the data from the peripherals. this shows me that writes are working correctly.

    using signal probe and interfacing directly to the data bus from a peripheral i can see that when reads are done, the correct information is at least arriving at the pins of the fpga. this tells me that the control signals going to the ram peripheral are working correctly.

    i don&#39;t know a whole lot about the avalon bus architecture or the "avalon_slave_arbitrator" that the data bus interfaces to so i was wondering at some other signals internal to the avalon that i could look at for proper operation? thanks!

    <div align='right'><{post_snapback}> (index.php?act=findpost&pid=19312)

    --- quote end ---

    --- Quote End ---