Avalon Bus not working after Upgrade

Update:

By writing to certain peripherals with a "non-working" load and then reconfiguring the FPGA with a working load, I can read back the data from the peripherals. This shows me that writes are working correctly.

Using Signal Probe and interfacing directly to the data bus from a peripheral I can see that when reads are done, the correct information is at least arriving at the pins of the FPGA. This tells me that the control signals going to the ram peripheral are working correctly.

I don't know a whole lot about the avalon bus architecture or the "avalon_slave_arbitrator" that the data bus interfaces to so I was wondering at some other signals internal to the avalon that I could look at for proper operation? Thanks!