Honored Contributor
Honored ContributorIf you are familiar with Signal Tap or Signal Probe, you can dig into the Avalon interface for your peripheral. Assuming your peripheral uses fixed timing (no wait signal), you should find three signals of interest on the Avalon interface for probing: a chip select, a read strobe, and read data. (The chip select and read strobe may be either positive or negative polarity, but you should be able to tell by the signal name.) The read access is pretty standard: chip select asserted, read strobe asserted (can be concurrent with chip select), and the data is sampled at the end of the cycle.
--- Quote Start --- originally posted by sph147@Nov 8 2006, 06:56 PM update:
by writing to certain peripherals with a "non-working" load and then reconfiguring the fpga with a working load, i can read back the data from the peripherals. this shows me that writes are working correctly.
using signal probe and interfacing directly to the data bus from a peripheral i can see that when reads are done, the correct information is at least arriving at the pins of the fpga. this tells me that the control signals going to the ram peripheral are working correctly.
i don't know a whole lot about the avalon bus architecture or the "avalon_slave_arbitrator" that the data bus interfaces to so i was wondering at some other signals internal to the avalon that i could look at for proper operation? thanks!
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