Honored ContributorIt is possible to create a component (ex. UART) with avalon MM slave interface with 8 bit data width and use it with Nios II with 32 bit bus?
I tried and compile fine but Nios II don't start on real fpga.. Thank you
Honored ContributorYes, it is possible. It should work fine.
Honored ContributorTricks was that instead of IORD and IOWR, 8 bit version IORD_8DIRECT and IOWR_8DIRECT should be used ;)
Honored ContributorHowever, in practise, you don't want to do it.
Instead create a 32bit slave that ignores the high bits on writes and returns zeros on reads. Remembering to look at the byte enables. If you have an 8bit slave you'll get a bus width adapter added than generates 4 cycles to your slave for every access done by the nios. Also, since the nios always asserts all 4 byte enables on reads, the data fifo probably work work properly.Honored ContributorThank you for your tips, i'm in a learning stage for qsys systems
Honored ContributorHonored ContributorAs as far as I know the nios always asserts all 4 byte enables on reads - and discards the unwanted bytes later.
The bus width adapters are also well known for generating master cycles with no asserted byte enables. If you also end up with a clock crossing bridge the transfers get very slow indeed.Honored Contributor
int alt_main(void)
{
for(;;) {
IORD_8DIRECT(SLAVE_8BIT_BASE, 0x10);
IORD_8DIRECT(SLAVE_16BIT_BASE, 0x10);
IORD_8DIRECT(SLAVE_32BIT_BASE, 0x10);
IORD_16DIRECT(SLAVE_8BIT_BASE, 0x10);
IORD_16DIRECT(SLAVE_16BIT_BASE, 0x10);
IORD_16DIRECT(SLAVE_32BIT_BASE, 0x10);
IORD_32DIRECT(SLAVE_8BIT_BASE, 0x10);
IORD_32DIRECT(SLAVE_16BIT_BASE, 0x10);
IORD_32DIRECT(SLAVE_32BIT_BASE, 0x10);
}
}
It actually looks as though the bus width adapter is asserting 'byte enable' but not asserting 'read' during the extra cycles.
The nios is definitely documented as always doing 32bit reads (ie asserting all 4 byte enables) Of course that might have changed - I don't remember us tracing them.Honored ContributorAttached is updated waveform with the NIOS data master Avalon signals expanded, where you'll see it is correctly issuing reads with 1,2,4 bytes enabled; the bus width adapter isn't doing much if anything.
Where do you see that the NIOS is definitely documented as always doing 32-bit access? The instruction set reference (ldbuio, ldhuio, ldwio) is pretty clear on what it is advertising, and I tend to agree with it based on my experiences.Honored ContributorTry using signaltap to look at a real nios rather than using the simulator, or at least run the gate-level simulator talking to avalon slaves.
TCM is read every clock regardless of the instruction type. I can't find the actual note about reads, but under 'Data Master Port' in Chapter 2 of the processor reference (page 2-11 in the 9.0 version I've got an 'dead tree') it states "Byte-enable signals on the master port specify which of the four byte-lane(s) to write during store operations." - nothing is mentioned about reads.
