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As as far as I know the nios always asserts all 4 byte enables on reads - and discards the unwanted bytes later.
The bus width adapters are also well known for generating master cycles with no asserted byte enables.
If you also end up with a clock crossing bridge the transfers get very slow indeed.
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While it may be possible to create a broken system as you describe, or possibly it was a rule of thumb with older tools --- at least with Qsys your described behavior is not true. I think it must "work correctly" since Quartus 12 as that is where I implemented a bursting 8-bit slave and didn't run into the issue at that time.
To test it again, I just created a dummy system in 14.0 with 8/16/32-bit slaves and a NIOS running this program:
int alt_main(void)
{
for(;;) {
IORD_8DIRECT(SLAVE_8BIT_BASE, 0x10);
IORD_8DIRECT(SLAVE_16BIT_BASE, 0x10);
IORD_8DIRECT(SLAVE_32BIT_BASE, 0x10);
IORD_16DIRECT(SLAVE_8BIT_BASE, 0x10);
IORD_16DIRECT(SLAVE_16BIT_BASE, 0x10);
IORD_16DIRECT(SLAVE_32BIT_BASE, 0x10);
IORD_32DIRECT(SLAVE_8BIT_BASE, 0x10);
IORD_32DIRECT(SLAVE_16BIT_BASE, 0x10);
IORD_32DIRECT(SLAVE_32BIT_BASE, 0x10);
}
}
Attached is the waveform.
You'll see the 8-bit slave correctly get hit for 1/2/4 transactions.
You'll see the 32-bit slave correctly get hit for 1 transaction with 1, 2, or 4 byteenables set.
You'll see the 16-bit slave correctly get hit for one or two transactions with 1 or 2 byteenables set.
In other words, it all kind of works like you would expect for a processor with dedicated byte/halfword/word {load,store} instructions and at least Qsys by default doesn't break anything.
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