Any example Master Ports available?

Hi Kerri,

Thanks for the help. I contacted a local FAE today and he had me zip my project to move it up the Altera line.

In the meantime we're going to try a less sexy solution and wire up a lpm_fifo to a normal memory port and IRQ on AlmostFull.

I really wanted a more elegant solution like Streaming DMA or Master Port, but if it works... I did have to give up 1K of instructions cache for the fifo, and it's not working yet either. Maybe in a day or two I'll know. (just built it a few hours ago - need to modify a little firmware to support it)

Maybe someone in Altera will come through with a fix for the MasterPort project I sent in.

Ken

Hi Kerry,

Any luck finding an example?

Thanks,

Ken

No, not yet.

If you want to send what you sent youe FAE, you can send it to me at khallbec@altera.com

Kerri

Hi Ken,

You'll get an email from me shortly. I rounded up several examples, but they are not in a state where I'd want to post them to the forum (lacking proper readmes/writeups/test software, etc). However I think they may help you out...

Thanks guys. I guess I'm just dense or not being very clear. (or both)

I've got a simple Master Port that I defined in SOPC builder that my external logic attempts to write into. It has only WEn, data[31..0], and address[31..0] for inputs and only wait_request for an output.

So my external logic puts address and data on the bus and pulls WEn low and then waits for the next rising clock where wait_request is not asserted. (We've tried every conceivable combination of always waiting for wait_request, asserting our signals on edges etc.)

Anyway, is there any reason our master shouldn't be able to write into sdram as fast as say a Nios processor? Our external logic writing through the master port works without flaw at fmax of 50 but gets say a 1-5% error rate at our required 75MHz. Of course an error rate of 0% is required.

Our master port is exactly like the example documented in the Avalon bus spec.(example 13, page 53) I was hoping for a working example like that.

I appreciate the components you sent me Jesse, but they have in excess of 30 ports to assign and I dont' really have a clue about 25 or so of them.

Are you saying our external logic will need to interact with the Avalon bus through this many signals as opposed to the simple (almost working) list provided by SOPC builder? I don't see these signals even referenced in the Avalon spec. The spec reads more like the list we're using as noted above.

I'm sure my lack of knowlege is the problem here, but its pretty darn close to working for me to have missed the boat by that much.

Thanks for the offer Kerri. I'll email my zipped project.

Maybe this description of the troubled port will help.

Thanks,

Ken

I've done a master-drives-Avalon port like this before, but at a much lower bandwidth. Basically, it was a bridge from a TI TMS320C55xx EMIF port (asynchronous) to the Avalon. I didn't use any signals besides those you're using plus read and readdata.

Most of the bridge was a set of registers which resynchronized the asynchronous requests, asserted wait states as long as necessary, and ran the requested cycle on the Avalon bus. Maximum read bandwidth was about 10% of Avalon bandwidth, since the synchronization network was about three registers deep (think dual-clock FIFO) each way. But it worked without error. Writing was about twice as fast, since things only had to happen one way in the FIFO.

If you want to use Streaming DMA, you have to use a bunch of other signals. That's probably what was going on in those examples you were sent. It begs the question, where is this 8MB/s coming from? Another processor? A state machine? An ADC?

Hi Mike,

The data is coming from an ADC at one 32 bit word every 570ns. The max it would ever be is 2MHz.

The MP writes each word into the port with an address pointing somewhere in sdram. (same sdram as Cyclone devkit)

Like I said it works without flaw at a CPUCLK of 50MHz but not at the required 75MHz. It works at 75MHz for a short while but always locks the bus.

Since it works at a lower fmax and we're not really burdening the system that much I'm kinda lost.

I kinda suspect that the build process optimizes the conection between our external logic and the avalon/sdram to the extent that they are too intermingled. We don't have any of this problem with logic that is actually outside the Cyclone chip. (where logical interfaces *must* be adhered to)

Any ideas?

Thanks,

Ken

Hi Kerri,

Jesse sent me example components but no working examples that use a UDL Master Port. I'm still looking at the ip_checksum example however. Is the point that bringing the UDL inside the SOPC system gives it better access to the Avalon bus than working through a UDL Master Port?

My case is just like example 13 on page 53 of the Avalon Spec. Mike described it perfectly with Master-drives-Avalon port phrase.

Did you get my project? The Master port is the SCAN_IN port. I annotated the bdf to point out the relevent blocks and signals.

Thanks,

Ken