Any example Master Ports available?

Hi Mike,

The data is coming from an ADC at one 32 bit word every 570ns. The max it would ever be is 2MHz.

The MP writes each word into the port with an address pointing somewhere in sdram. (same sdram as Cyclone devkit)

Like I said it works without flaw at a CPUCLK of 50MHz but not at the required 75MHz. It works at 75MHz for a short while but always locks the bus.

Since it works at a lower fmax and we're not really burdening the system that much I'm kinda lost.

I kinda suspect that the build process optimizes the conection between our external logic and the avalon/sdram to the extent that they are too intermingled. We don't have any of this problem with logic that is actually outside the Cyclone chip. (where logical interfaces *must* be adhered to)

Any ideas?

Thanks,

Ken