Honored Contributor
Honored ContributorI've done a master-drives-Avalon port like this before, but at a much lower bandwidth. Basically, it was a bridge from a TI TMS320C55xx EMIF port (asynchronous) to the Avalon. I didn't use any signals besides those you're using plus read and readdata.
Most of the bridge was a set of registers which resynchronized the asynchronous requests, asserted wait states as long as necessary, and ran the requested cycle on the Avalon bus. Maximum read bandwidth was about 10% of Avalon bandwidth, since the synchronization network was about three registers deep (think dual-clock FIFO) each way. But it worked without error. Writing was about twice as fast, since things only had to happen one way in the FIFO. If you want to use Streaming DMA, you have to use a bunch of other signals. That's probably what was going on in those examples you were sent. It begs the question, where is this 8MB/s coming from? Another processor? A state machine? An ADC?
