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3LionsCT's avatar
3LionsCT
Icon for Occasional Contributor rankOccasional Contributor
2 months ago

Address Space?

Hi 

I am confused about the address space requirements when using your own Avalon master in a custom module. (see attached)

Why do I have to use more address bits than I need when I only drive one module. It appears that  I have to add 2 extra bits to my address space for every module I go through to account for the interconnection fabric. This means that the address I generate has to be 28 bits instead of the 24 bits I need to address the RAM

I know it is probably something stupid I am doing here. What am I missing?

Thanks for the help

layer

12 Replies

  • sstrell's avatar
    sstrell
    Icon for Super Contributor rankSuper Contributor
    1 month ago

    Also, you don't need to create custom arbitration logic.  The interconnect builds arbitration logic for you.

    • 3LionsCT's avatar
      3LionsCT
      Icon for Occasional Contributor rankOccasional Contributor
      1 month ago

      I believe it is 32 bits. I've attached the address map.

       

      Could the extra two bits have anything to do with using a 32 bit address bus so the Address bus needs an extra two bits for the bye offsets?

      Thanks

      • ShengN_altera's avatar
        ShengN_altera
        Icon for Super Contributor rankSuper Contributor
        1 month ago

        May I know if the arbiter module is not used, the custom hdl min address width is?