Occasional Contributor
Occasional ContributorI believe it is 32 bits. I've attached the address map.
Could the extra two bits have anything to do with using a 32 bit address bus so the Address bus needs an extra two bits for the bye offsets?
Thanks
Super ContributorMay I know if the arbiter module is not used, the custom hdl min address width is?
Occasional ContributorThe arbiter module is used. I attached a sketch of the system with the address widths. Basically I am trying to access a common sdram from both the Nios V and my own custom HDL
Thanks
Super ContributorI mean if you don't use the arbiter module but straight connect both Nios V and custom HDL to sdram what happen to the minimum address width?
You can use platform designer arbitration logic https://docs.altera.com/r/docs/683609/25.1.1/quartus-prime-pro-edition-user-guide-platform-designer/arbitration
Occasional ContributorI haven't had time to do as you suggest yet
The reason I built my own arbiter was that I wanted to make sure that the custom hdl could prevent the nios v from accessing the sdram which it was in control
