access to every address of SDRAM

Actually the nios cpu always requests 32bit reads - and discards the unwanted bytes itself, rather than (also) asserting the relevant byte enable line(s).

If you have an 8bit slave, a 'bus width adapter' is used to convert the 32bit access into four 8bit ones. IIRC these copy over the byte enables from the original request - but don't skip the cycles that have no asserted byte enabled.

These extra cycles show up as a measureable delay, especially when clock crossing bridge in included. They also cause much confusion when the bus master is the PCIe block - which always does 64bit slave accesses.