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Altera_Forum
Honored Contributor
Honored Contributorabout the NIOS II IDE
About the Address of the TIMER_CONTROL and TIMER_STATUS:
in my SOPCBUILD, the TIMER_0_BASE = 0x4800(18432) So ,I think the address: TIMER_CONTROL: 0x4800(18432)+2 = 0x4800(18432)+2 TIMER_STATUS: 0x4800(18432)+0 = 0x4800(18432)+0 But one the DISASSEMBLY , I find the TIMER_CONTROL`s address if 18436(0x4800+4) So , how to switch the bus width between 32bit and 16bit, and the function of IOWR_ALTERA_AVALON_TIMER_CONTROL() is 32bit ??? think you ,for your help??? DISASSEMBLY: IOWR_ALTERA_AVALON_TIMER_CONTROL(TIMER_0_BASE, 0x00000244 <init_timer_0+16>: movi r3,18436 http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/ohmy.gif 0x00000248 <init_timer_0+20>: movi r2,7 0x0000024c <init_timer_0+24>: stwio r2,0(r3) np_timercontrol_start_mask | np_timercontrol_cont_mask | np_timercontrol_ito_mask ); IOWR_ALTERA_AVALON_TIMER_STATUS(TIMER_0_BASE, 0x00000250 <init_timer_0+28>: movi r3,18432 http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/ohmy.gif 0x00000254 <init_timer_0+32>: movi r2,3 0x00000258 <init_timer_0+36>: stwio r2,0(r3) np_timerstatus_run_mask | np_timerstatus_to_mask);4 Replies
Altera_ForumHi xc214043,
> But one the DISASSEMBLY , I find the TIMER_CONTROL`s address if 18436(0x4800+4) This is correct ... the registers are all 32-bit aligned. status @ base + 0x00 control @ base + 0x04 periodl @ base + 0x08 and so on. > IOWR_ALTERA_AVALON_TIMER_CONTROL(TIMER_0_BASE, > 0x00000244 <init_timer_0+16>: movi r3,18436 ; 0x4804 (base + 4) -- correct > IOWR_ALTERA_AVALON_TIMER_STATUS(TIMER_0_BASE, > 0x00000250 <init_timer_0+28>: movi r3,18432 ; 0x4800 (base + 0) -- correct Regards, --Scott- Altera_Forum
smcnutt, thank you for your help
because in some resource, it told me the_timer is 16-bit aligned, so i think status @ base + 0x00 control @ base + 0x02 periodl @ base + 0x04 now, i am puzzle. can you give me some imformation about this thanks!! - Altera_Forum
Hi xc214043,
> because in some resource, it told me the_timer is 16-bit aligned, so i think You're probably referring to the "Nios II Altera Embedded Periperals Handbook", which shows the registers as being 16-bit -- and they are 16-bit registers. However, each 16-bit register is mapped to a 32-bit word ... the registers are aligned on 32-bit boundardies. > now, i am puzzle. > > can you give me some imformation about this Open your ptf file in a text editor and take a look at the timer module. You should see the following:
Then get a copy of "Quartus II Handbook, Volume 4, SOPC Builder" and read the section entitled, " Native Address Alignment & Dynamic Bus Sizing" in chapter 3. Specifically, look at Table 3-2. This should answer all of your questions. Regards, --ScottAddress_Alignment = "native"; Data_Width = "16"; - Altera_Forum
Hi smcnutt
--- Quote Start --- originally posted by smcnutt@Aug 15 2005, 06:44 AM each 16-bit register is mappedto a 32-bit word ... the registers are aligned on 32-bit boundardies.
--- Quote End --- en ,i see thank you for your help, very.very.... http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/rolleyes.gifaddress_alignment = "native"; data_width = "16";
