about the NIOS II IDE

Hi xc214043,

> because in some resource, it told me the_timer is 16-bit aligned, so i think

You're probably referring to the "Nios II Altera Embedded Periperals Handbook", which shows the

registers as being 16-bit -- and they are 16-bit registers. However, each 16-bit register is mapped

to a 32-bit word ... the registers are aligned on 32-bit boundardies.

> now, i am puzzle.

>

> can you give me some imformation about this

Open your ptf file in a text editor and take a look at the timer module. You should see the following:

Address_Alignment = "native";
Data_Width = "16";

Then get a copy of "Quartus II Handbook, Volume 4, SOPC Builder" and read the section entitled,

" Native Address Alignment & Dynamic Bus Sizing" in chapter 3. Specifically, look at Table 3-2. This

should answer all of your questions.

Regards,

--Scott