New ContributorAbout："Nios II Processor Booting From Altera Serial Flash（EPCQ）"
Q1:
The 14th page describes how to generate the .jic file. Here is a diagram where the added hex file is specified by a relative address and named epcq_controller.hex. If it is in the Boot Copier Method, does epcq_controller.hex already include the boot copier? Regarding the Execute-In-Place Method, the third page describes a RAM; is it necessary to additionally add this RAM in qsys?
Q2:
The 6th page of the document describes setting the offset address for the Reset Vector, which is illustrated as 0x01E00000 in the example. On the 15th page, it explains the scenario of setting relative addresses in the .hex file. I'm not quite clear on the significance of "You may select Relative addressing if you would like to set a relative address to the reset vector offset (0x01E00000) you configured earlier. For example, setting a start address of 0x01F00000 for the relative addressing mode changes the start address to 0x3D00000."
The input of 0x01F00000 here, what impact does it have, and is it related to the address set in the .sof file? How is 0x01F00000 determined?
