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Yordles_Heart's avatar
Yordles_Heart
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2 years ago

About："Nios II Processor Booting From Altera Serial Flash（EPCQ）"

Q1: The 14th page describes how to generate the .jic file. Here is a diagram where the added hex file is specified by a relative address and named epcq_controller.hex. If it is in the Boot Copier Me...
Embedded Applications Layer
wwanalim_intel's avatar
wwanalim_intel
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2 years ago

If it related to that document.


Q1 - Yes. It is essential to include RAM in Qsys since that is where the application is stored.

Q2 - It is an optional to use the relative addressing. Usually using the absolute addressing as at the end of the tutorial also using absolute. The address 0x01F00000 will add to the end address of SOF. Using relative addressing will need to compile SOF, generate JIC, check MAP modify the reset vector recompile SOF and regenerate JIC.

Below inserted additional information.

Reset vector - https://www.intel.com/content/www/us/en/docs/programmable/726952/23-4/hardware-design-flow-15362.html

Absolute addressing - https://www.intel.com/content/www/us/en/docs/programmable/726952/23-4/programming-files-generation-04026.html