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Altera_Forum's avatar
Altera_Forum
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15 years ago

A_en is 'X' problems

Hi there, i have wrote some VHDL program in QuartusII (10.1)as custom instruction for NIOSII and implemented a SOPC system with Nios II. Then i go to the EDA (eclipse) generate a hallo world progr...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Cured by setting up reset and clk signals correctly before simulating. I left them in the default state and they need forcing..

for example

force reset 1, 0 40

force clk 1, 0 10 -repeat 20

This is true for Qsys simulations at least.