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Altera_Forum
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15 years ago

A_en is 'X' problems

Hi there, i have wrote some VHDL program in QuartusII (10.1)as custom instruction for NIOSII and implemented a SOPC system with Nios II. Then i go to the EDA (eclipse) generate a hallo world progr...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

It's a pipeline enable for the 'Align' stage of the processor pipeline. The processor simulation files are coded to catch cases where unknown values trickle through the pipeline.