A_en is 'X' problems

Hi there,

i have wrote some VHDL program in QuartusII (10.1)as custom instruction for NIOSII and implemented a SOPC system with Nios II. Then i go to the EDA (eclipse) generate a hallo world program and run it in Modelsim(6.4b). And everything is ok untill this error pop up in modelsim:

# 314830 ns: ERROR: NIOS_test_bench/A_en is 'x'# ** Failure: VHDL STOP# Time: 314830 ns Iteration: 1 Process: /test_bench/dut/the_nios/the_nios_test_bench/#MERGED#line__877,842,786,768,731,713,695,677,641,623,605,587,531,494 File: /home/Desktop/dct_transform/NIOS_test_bench.vhd# Break in Architecture europa at /home/Desktop/dct_transform/NIOS_test_bench.vhd line 598

and the relative Code is generated automatically by SOPC builder :

process (clk)

VARIABLE write_line5 : line;

begin

if clk'event and clk = '1' then

if std_logic'(reset_n) = '1' then

if is_x(std_ulogic(A_en)) then

write(write_line5, now);

write(write_line5, string'(": "));

write(write_line5, string'("ERROR: NIOS_test_bench/A_en is 'x'"));

write(output, write_line5.all & CR);

deallocate (write_line5);

assert false report "VHDL STOP" severity failure;

end if;

end if;

end if;

end process;

ok, please help!!!:(