Honored ContributorHello,
I would like to know if we can increase the FMax of the board. I would like to reach the MAX frequency can support the board. How can I do it? The reference design has implemented a 50 MHz. Is that possible to increase it? Best regards Christian
Honored ContributorYes it's a hardware change (increase the clock frequency, and re-build the NIOS with the new frequency)
Honored Contributorguess that wasn't enough info.
Using a PLL on you're device, the input clock (50Mhz) can be scaled to many different frequencies. Don't expect something like 400MHz because that's just not possible, but 100Mhz is quite doable. G-luckHonored ContributorThank you,
I'll try to increase the PLL frequency to reach 100 MHz. ChristianHonored ContributorI'm barely reaching an Fmax of 100MHz with the 1S10 (ES) NIOS development board using the "s" core, so you might want to target the "f" core if that's an option. With the 'f" core you can probably reach 125MHz easy if your surrounding logic doesn't not drag down the NIOS core.
The 's' core is constricted to around 100MHz on the paths through the ALU (hardware multiply, shifting, etc....) Is there some Quartus optimization that I should try since my target is 100MHz, and I was able to make the "s" model keep up to the full one (I want to save 400LEs) CheersHonored ContributorHonored ContributorI thought increasing fmax was a typo, but it actually did improve it. Thanks you may have saved me a lot of LEs http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/smile.gif
CheersHonored ContributorIf you really need more fmax then /e is the way to go. The current issue of Alteras newsletter has a complete table of chips and NII cores and fmax's.
They show the /e going 201MHz on Stratix II. For Stratix I they show 141MHz for /f, 130 for /s, and 144 for /e. For Cyclone I got NiosI going 140 all internal, 120 with SDRAM as data only, and 110 running out of SDRAM. Don't plan on these speeds in your real world app though. Once I added all the required peripherals to the Avalon bus (and complex firmware) I'm down to 75. KenHonored ContributorI'm restricted to a system speed of 100Mhz, but I also need high performance out of the NIOS as well. I found very little difference in speed between the 's' and 'f' models due to the nature of the design. The 's' model was used as an attempt to reduce the logic size since the overall design will be very busy. Right now the design is pretty light, just a NIOS and some surrounding logic, so I expected at least 110Mhz from the 's' core seeing as it's "suppose" to have an Fmax of 130 on stratix.
So it's not that I want to increase my system past 100MHz, I just don't like the idea of a light system having an fmax of 100Mhz since it's going into a much larger design. This is also the first time I've ever seen a NIOS having a low fmax due to internal logic (usually it's when you attach other hardware to the NIOS or put it into a busy design).Honored Contributorwhat are the few other little peripherals?
If any are off chip, it will slow things down. What have you configured into the niosII? any debug?Honored ContributorIt's a pretty plain system right now. Everything is contained within the FPGA. So their is logic added to do communication across the custom hardware interface, and I added a hardware divider that I created (since that core doesn't have one). The divider on it's own has an Fmax of 150, and after the timing analysis is complete is not part of any critical paths when used by the NIOS. The critical paths are all in the ALU, and I'm finding the logic in the messages having names like MUL, pipeline, shift (if I remember correctly, I'm re-building right now so that I can get the exact names). Also to rule out my divider, I've put it into the 'f' core and turned off the Altera provided one, and my timing and processing performance is not affected at all.
When I use the 'f' core then the NIOS is simply restricted in fmax by some of my surrounding logic (and the fmax is what I'm expecting). So I have a perfectly fine system using the 'f' core, but it's a bit overkill for what I need, and I'm able to get almost identical performance out of the 's' core due to my design. But I'm not going to trust my design running on the 's' core until that fmax is at least 10Mhz higher since this design will be dropped into a much larger design. Is it possible that the ALU has problems targetting the 1S10ES device? (NIOS development board). Thank-you for you're help and any additional insight you may have. *Edit* I've been using the minimal debug capabilities to download code. I'm starting a build without it to see what happens.
