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kh99's avatar
kh99
Icon for New Contributor rankNew Contributor
1 year ago

19.1 Nios II firmware and hardware ported from 15.1 external sram self test fails

Cyclone V FPGA and Nios II firmware source originally developed and working on Quartus 15.1 has been ported to Quartus 19.1. A firmware loader executing from parallel flash writes and reads patterns...
Embedded Applications Layer
Nios Cpu
tehjingy_Altera's avatar
tehjingy_Altera
Icon for Regular Contributor rankRegular Contributor
1 year ago

HI


A suggestion could you try adding a delay in the c code? like a 5 second delay as a test before doing any sram test?

This is to ensure that the EMIF have completed the calibration before any read/write to the sram.


Regards

JIngyang, Teh


  • kh99's avatar
    kh99
    Icon for New Contributor rankNew Contributor
    1 year ago

    Hi Jingyang,

    We added the "JTAG to Avalon Master Bridge" and used system console to verify that the first 0x3000 hex bytes of sram could be written, read, and verified. Adding the 5 second delay didn't help.

    I believe I've found what caused the issue, it's firmware related. Am testing now to verify this.

    Thanks for your help.