Forum Discussion
Honored Contributor.elf file explained?
Hello!
I have just watched the ALTERA Embedded Design Flow video tutorial and at some point at the end it is explained how the user can program a flash memory with: - A boot loader - The FPGA .sof image - The .elf file and I was wondering what is the structure of a sof file (less important for me) and most important what is the structure of an .elf file. I mean after the compilation there are stack, heap, code and data segments? And what does each of them represent? Also Is the elf file directly copied as is into the flash or is it restructured before saved to flash (in other words does Nios execute the actual elf file as it is?)?22 Replies
Altera_ForumELF stands for Executable and Linkable Format
If you google, you should be able to find lots of information about this file format.- Altera_Forum
Yes I know that but I am not sure if it applies also for the Nios processor. Is there any dump command indise the EDS to handle/see/dump elf files?
- Altera_Forum
For your other question, .ELF is converted to .flash (Motorola S-Record).
The .POF (Programming Object File) is special from Altera to their FPGA. You might not find information about the structure. But altera give tools to create a .pof with the .sof(to configure fpga), and flash (with special boot loader). That is in the tutorial you are reading. You download the .POF to an EPCS serial memory. So it will be size-limited (the size is not a constant because of an eventual "compression"). Nios can execute the .ELF as is. This is what you do when you "Ran as hardware" from Eclipse NIOS II SBT. It executes from RAM directly. When the program is in FLASH, the boot loader tells NIOS to first copy the content to RAM and then Nios executes from the RAM. - Altera_Forum
Hey thank you!!
So in my Qsys system I only need to insert an external SDRAM interface module as far as the memories are concerned. I shouldnt insert an on chip ram for the heap and stack as they will be included inside the same external SDRAM. The copying of the program from the flash to the RAM (boot loader) is done by Nios? If so should I include an EEPROM memory interface inside the Qsys system? (I am using the DE0-Nano board so I have a 32MB external SDRAM, an external 2KB I2C EEPROM and a non-accessible from user code 16MB EPCS EEPROM) - Altera_Forum
The simple altera examples use a single memory block for code, data, heap and stack.
Probably because this is the easiest one to explain and demostrate in any training. Depending on what you actually intend doing, a lot of these examples aren't (IMHO) especially useful. - Altera_Forum
Haha I liked the IMHO (In My Humble Opinion), never heard it before!!
Basically my application is not very demanding. I just need to have everything (.SOF, .ELF running only in SDRAM plus heap stack also in SDRAM) stored in the EPCS and on-power on the FPGA gets configured and the Nios starts reading instructions from the SDRAM. If this operation involves a boot loader that is created automatically and does not need me to incorporate the EEPROM interface so as to copy the elf to SDRAM then it fits me well. Is this process automatic? - Altera_Forum
AFAIK (As Far As I Know :-D) the Boot Loader is executed by NIOS. So you need to incorporate a EPCS (on which you want to store FPGA config, ELF or equivalant for programm, and special boot loader) interface. I saw this interface in Altera QSYS components, but never tried.
I saw a few examples that do that. There is a "default" boot loader from Nios II SBT. Look at http://www.alterawiki.com/wiki/epcs_bootloaders AFAIK, IMHO, BTW..... and RTFM (= "Read The F°ck1ng Manual !" :-D) - Altera_Forum
Wow....
I need an interface for the EEPROM (EPCS). The thing is that I have a DE0 Nano and the EPCS is not available for user code (only for initial FPGA configuration). I am also a RTFM guy but the problem is that there is such a plethora of tutorials, applications notes, manuals, userguides etc etc etc .....and videos that don't get me wrong here but most of them only scratch the surface in between the marketing power point bullet lists (ssshhhhhh....). So there is also an altera wiki site. Thats good. - Altera_Forum
After initial FPGA configuration, the EPCS can be accessed through the EPCS serial flash controller.
The Qsys ECPS serial flash controller will also contain the bootloader code required to copy the data from the flash to the SDRAM. - Altera_Forum
Hey thanks for the answer. But what are the pins that DE0 Nano gives the user to access the EPCS? I didn't see any in the manual...
