a. sounds like the wrong memory is being targetted (can you provide more information like what memory (type and size) you have in your hardware and what memory targets are being used in the system library project (right click the project and select properties))
b. you are correct about the soft emulation of a FPU. However, since FPGAs are meant to hold user defined logic you are in luck. Nios II (and Nios I) have the ability to use "Custom Instructions". A custom instruction (CI) allows the user to add their own logic to the Nios ALU. So a Nios ALU has things like add, subtract, compare, rotate, multiply, etc... and you can add your own logic to expand it's functionality. By the way if you go to the IP section of this forum, there is a floating point unit available there.
Depending on what you are trying to do perhaps you would not want to use a CI and instead create an Avalon slave to do the calculations (you won't be stalling the CPU while it executes the CI). With that approach you just keep blasting values into it and can even allow it to send them off to the filter.
I have a question though. Are your coeffs going to be floating or fixed point when used with the DSP logic? If they are going to be fixed point in the end I recommend creating an external wide co-processor to handle the large interger calculations.
What you are trying to do (if I understood correctly) is a pretty common use of a Nios processor in many FPGA based DSP designs.
Honored Contributor
