Honored ContributorHi,
I am wondering if it is possible to implement a µCLinux in a Stratix GX Development Board? In fact, I have a Stratix GX Development Board in order to develop high speed applications. Don't worry, the Nios will not be used for high speed applications! Let me know your thoughts about that. Thanks a lot. Freechip.
Honored Contributori use windows environment. now i have problems with sopc builder and system generating. i have on my board 256mb ddr 333mhz cl2.5, but i think you can buy even faster ddr ram 400mhz.
<div align='right'><{post_snapback}> (index.php?act=findpost&pid=15439)
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--- Quote End --- Ok, thanks but on the High Speed User Guide, it is mentioned that the frequency of the DDR must be 166Mhz or 200Mhz and Altera told me it is impossible to take higher frequency than 200Mhz. So I am surprised by your answer. Tell me what you think about that. Thanks. Freechip.
Honored Contributor--- quote start ---
<!--quotebegin-macio@May 18 2006, 04:25 AM hi,
i use windows environment. now i have problems with sopc builder and system generating. i have on my board 256mb ddr 333mhz cl2.5, but i think you can buy even faster ddr ram 400mhz.
<div align='right'><{post_snapback}> (index.php?act=findpost&pid=15439)
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--- Quote End --- Ok, thanks but on the High Speed User Guide, it is mentioned that the frequency of the DDR must be 166Mhz or 200Mhz and Altera told me it is impossible to take higher frequency than 200Mhz. So I am surprised by your answer. Tell me what you think about that. Thanks. Freechip. <div align='right'><{post_snapback}> (index.php?act=findpost&pid=15443)</div> [/b] --- Quote End --- I meant DDR 400. Its clock frequency is 200MHz but both edges are active. You can check it in "DDR & DDR2 SDRAM Controller Compiler User Guide" on page 3-49 there is hardware testing and there is shown in the table what type of memory was tested on that board.
Honored ContributorOk for your answer.
What is the size of your DDR SDRAM (128 MB, 256 MB...)? Because it is very difficult to find DDR SDRAM 128 MB 200Mhz. I am wondering if I can connect DDR SDRAM 256 MB 200Mhz. Sorry for these details. ThanksHonored ContributorMacio,
I have found an answer to your problem. (DDR Controller error with Stratix GX Device). http://www.altera.com/support/kdb/solution...022005_688.html (http://www.altera.com/support/kdb/solutions/rd12022005_688.html) FreechipHonored Contributori have found an answer to your problem. (ddr controller error with stratix gx device).
http://www.altera.com/support/kdb/solution...022005_688.html (http://www.altera.com/support/kdb/solutions/rd12022005_688.html)
freechip
<div align='right'><{post_snapback}> (index.php?act=findpost&pid=15462)
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--- Quote End --- Thanks a lot Freechip. It was solution of my problem. Unfortunately I have now compilation errors in Quartus, but I will try to solve this problem. As I wrote I have 256MB DDR SDRAM on my board. Nios can address only 256MB but you can change number of column address bits in DDR SDRAM Controller Megacore IP Toolbench from 10 bits to 9 bits. In that way only half of that memory will be used but you can add other peripherals to system and you won't have error "Address range of instruction master crosses 256-Mbyte".
Honored ContributorHi,
I have build hardware for Stratix GX development board without any error, but now I have problem with building uCLinux kernel. When I try to generate system.h# generate nios2_system.h from ptf
make ARCH=nios2nommu CROSS_COMPILE=nios2-linux-uclibc- hwselect SYSPTF=stratixGX.ptf--- Please select a device to execute kernel from:
(1) ddr_sdram
Class: ddr_sdram_component
Size: 0 bytesPlease zip your ptf and post it as attachment file in the buildroot guide thread.
Honored Contributori have build hardware for stratix gx development board without any error, but now i have problem with building uclinux kernel. when i try to generate system.h
# generate nios2_system.h from ptf
make arch=nios2nommu cross_compile=nios2-linux-uclibc- hwselect sysptf=stratixgx.ptfit detects that i have 0 bytes ddr_sdram
--- please select a device to execute kernel from:
(1) ddr_sdram
class: ddr_sdram_component
size: 0 bytessopc builder system consists of nios2 cpu, ddr sdram controller (base address 0x00000000, end address 0x07ffffff == 128mb ??), uart, jtag uart, timer, sysid, avalon tri state bridge and dummy cfi flash (not connected to any fpga pin). can anybody help me?
best regards,
maciek
<div align='right'><{post_snapback}> (index.php?act=findpost&pid=15551)</div> --- Quote End --- I had similar problem before. Your ddr core avalon data bus width is greater than 32 bits, and the hwselect script can't handle. Please edit the ptf for hwselect only (not for hardware generation), reduce data bus width to 32 bits, and increase address bus width (up to the ddr memory capacity) .
Honored Contributoryour ddr core avalon data bus width is greater than 32 bits, and the hwselect script can't handle.
please edit the ptf for hwselect only (not for hardware generation), reduce data bus width to 32 bits, and increase address bus width (up to the ddr memory capacity) .
<div align='right'><{post_snapback}> (index.php?act=findpost&pid=15575)
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--- Quote End --- Ok, that works. Thanks a lot Hippo!
