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Honored Contributor
Honored ContributorXAUI Tx lane reversal
Hi everyone, I designed a board with Arria V GX on it. I have mistakenly reversed (In relation to Rx) the XAUI Tx lanes on my new board. The compilation fails for the current pin layout. Whe...
Altera_ForumHonored Contributor
Honored ContributorHi Dror,
The XAUI PHY is not a simple Parallel to/from Serial converter. The PHY checks the incoming data stream to ensure that the character code transition follows IEEE802.3 Clause 48 state diagram. For example, Termination code (data=0xFD, ctrl=0x1) must be followed by Idle code (data=0x07, ctrl=0x1), otherwise the XAUI PHY IP recognizes the code transition is invalid. In your case, Idle is followed by Terminaiton, that is invalid, and then the PHY IP injected Error code (data=0xFE, ctrl=0x1) as an error flag. If simplex swap is not allowed, the board has to be re-designed unfortunately.
