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Altera_Forum
Honored Contributor
10 years agoXAUI Tx lane reversal
Hi everyone, I designed a board with Arria V GX on it. I have mistakenly reversed (In relation to Rx) the XAUI Tx lanes on my new board. The compilation fails for the current pin layout. Whe...
Altera_Forum
Honored Contributor
10 years agoHi,
Have you tried the assignment? You can find this in the Transceiver PHY IP User Guide. Example 7-1 shows how to remove the restriction on logical lane 0 channel assignment in Stratix V devices by redefining the pma_bonding_master parameter using the Quartus II Assignment Editor. In this example, the pma_bonding_master was originally assigned to physical channel 1. (The original assignment could also have been to physical channel 4.) The to parameter reassigns the pma_bonding_master to the XAUI instance name shown in quotation marks. You must substitute the instance name from your design for the instance name shown in quotation marks Example 7-1: Overriding Logical Lane 0 Channel Assignment Restrictions in Stratix V Devices set_parameter -name pma_bonding_master "\"1\"" -to "<xaui instance name>|sv_xcvr_xaui:alt_xaui_phy|sv_xcvr_low_latency_phy_nr: alt_pma_0|sv_xcvr_custom_native:sv_xcvr_custom_inst|sv_xcvr_native: gen.sv_xcvr_native_insts[0].gen_bonded_group.sv_xcvr_native_inst" Swapping parallel data bus wouldn't work because the XAUI PHY IP expects start-of-packet symbols come to Lane 0.