Forum Discussion
Altera_Forum
Honored Contributor
16 years agoHi clggrad,
You probably have already found a solution. I am not that familiar with Verilog, but what I can gather from your code is that you want a fair amount of processing to happen instantaniously and that each iteration depends on the results from the previous iteration. Although it may be possible to describe this as a huge blob of logic, it would probably not be very practical. A registered processing loop as you have implemented is a better approach since it allows you to re-use the resources. You can optimize the performance by unrolling the loop slightly (say 2 or 4 time). This way you will get an answer after 16 or 8 clock cycles. Regards, Niki