Honored Contributor
Honored Contributorhey sorry i couldnt reply earlier but thanks alot for the detailed reply.. niki.... i did end up getting it to work using flags and offsets.. :D
i am stuck at another place.. i know always stuck somewhere.. i want a piece of code to be repeated 32 times.. i obviously cant use while or for in verilog.. i have written the following for the whole process to repeat.. ///////////////////// code ///////////////////////////// always @ (posedge CLOCK_50) begin if(bit_1 < 32 && bit_1 >= 0) begin count_di <= 1; end else begin count_di <= 0; end end // of always.. for count //// the above part is for performing the while operation //// /////////// main code//////////// always @ (posedge CLOCK_50) // each 20nsec begin if(ready_di ==1 ) begin bit_1 = 6'd32; la = 0; la_temp = 0; ty_c = {32'd0,py1};//ty}; tx_c = {1'b0,px1,31'd0}; end if ( count_di != 0 ) begin diff = ty_c - tx_c; la_temp = la_temp << 1; if( !diff[63] ) begin ty_c = diff; la_temp[0] = 1'd1; end la = la_temp; tx_c = tx_c >> 1; bit_1 = bit_1 - 1'b1; end if(bit_1 == 0 && la >0) begin temp3= (la*la); temp4 = px1-qx1; qx1 = temp3 - temp4; end //////////////////// end of code///////////////////////// the above is the not the entire code just a subset of it .. my problem / doubt.. the above piece of code works fine and i am getting the output correct too.. but it doesnt happen all at once.. I mean when the configure thew FPGA and run Nios II.. I actually have to run Nios II 32 times to see the output..which is obviously not right. i want the whole loop to be done at once i hope u all understand what i m trying to say.. Please do help me out here.. Thanks again. you all are very helpful..
