Forum Discussion
Altera_Forum
Honored Contributor
17 years agoYou seem to understand why there is 12 bits of address lines to your component, but I think there is still some confusion on how the component is actually accessed.
To read 64 bits from you component, I think NIOS will perform this in two 32 bit cycles. Try synthesizing the simplest test case you can and then look at the RTL viewer. This can often clear up what is going on at a low level. I just tried this for a simple system with a NIOS processor and a 64 bit wide component. If you trace the 64 bit bus from the component, what you will find is that it is split into two 32 bit halves and fed input a 2:1 mux. The mux is controlled by bit 2 of the address bus.