Writing to SDR SDRAM through Synposys designware mem controller

Ok, in that case you can define all your timing constraints relative to the clock input and Timequest should say if they can be met. How did you define your constraints? Did you use this guide (http://www.alteraforum.com/forum/showthread.php?t=1269) ?

If you think there could be a delay between the clock seen from the RAM and the one seen from the FPGA, you can create a virtual clock in your SDC file, that is derived from the clock input on the FPGA, but with a delay to represent the clock on the RAM. And then do all your constraints relative to that virtual clock.