Writing to SDR SDRAM through Synposys designware mem controller

Actually, we cannot give the timing constraints with respect to the clock going out of design. Here in this case clock to sdram is sent from the design so I gave the constraint with respect to the clock whch is used to run the entire design. So, how can i verify the timing constraints of the sdram if i dont know how much the control signal transitions are delayed from the SDRAM clock. Both the input and SDRAM clock are synchronous and are same but after generation of SDRAM clock in the design to the PAD of the fpga the delay might be such that some of the address lines meet the setup and hold time requirements (i.e., they arrive 3ns before the SDRAM clock ) and some of the address lines arrive after the SDRAM clock. Is this point which I am making valid?