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Altera_Forum
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16 years ago

Writing to SDR SDRAM through Synposys designware mem controller

hi, When I am writing to sdram through synopsys designware memory controller the address is not being properly latched by the SDRAM. Like, if I give address as 0x0018 it will write to 0x0010(o...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

hi,

yeah, there are timing constraints and the timing constraints are met for all the signals. Except that the clock to sdram (generated in the design) has no timing constraint as the input clock does not clock data to this port.