Why won't PLL Reconfig IP allow access to cascaded tap?

I can't explain why this is happening. However, I can offer some thoughts.

Which device are you using? I'm surprised Quartus allows you to specify a clock out of 100kHz. Outputs are often restricted to something over 1MHz. However, it clearly works. My suspicion is that the cascade simply cannot be reconfigured and you're ending up with the lowest frequency that the PLL can generate.

Regardless of this I'd highly recommend not designing in this way. Operate your logic at a higher frequency and have a 100kHz 'tick' within your logic indicating when to run the circuitry that needs to operate at 100kHz. If you need a true, 50/50 mark/space ratio output signal, generate this in logic as well.

If, by reconfiguring your PLL, you need to move away from 100kHz, then adapt your logic as appropriate.

Cheers,

Alex