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XQSHEN's avatar
XQSHEN
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

Why this signal of ALTPLL is a base clk?

Why this signal of ALTPLL is a base clk?

IP: ALPLL

Quartua Prime 18.0 timing analyzer.

2 Replies

  • KennyT_altera's avatar
    KennyT_altera
    Icon for Super Contributor rankSuper Contributor
    5 years ago

    This happened usually you did not use the derive_PLL_clocks in your sdc files. Can you check your *.sdc?