XQSHENOccasional Contributor5 years agoWhy this signal of ALTPLL is a base clk? Why this signal of ALTPLL is a base clk? IP: ALPLL Quartua Prime 18.0 timing analyzer. Show More
Recent DiscussionsCascaded Avalon Stream Multiplexer in Platform Design does not forward valid data packetsCyclone V CAN triple samplingSolvedR_Tile PCIEAgilex 7 I F-Tile Direct PHY: example TB doesn't workSolvedWhy the Error Response Slave IP cannot work for Agilex 5 SOC FPGA?