XQSHENOccasional Contributor6 years agoWhy this signal of ALTPLL is a base clk? Why this signal of ALTPLL is a base clk? IP: ALPLL Quartua Prime 18.0 timing analyzer. Show More
Recent DiscussionsQueries on 46.6944 Gbps PAM4 F-Tile Configuration and Loopback Testing using Agilex7Request about FPGA 10CL025YU256A7GSolvedIEEE1588 Time of day IP - old Intel links are brokenTerasic P16E-FMCP PCIE Express 3.0 compatibility issues with AMD processorsIntroducing the Altera Community AI Responder — Beta
