Why there's no clock on afi_clk output of the Hard DDR3 Memory Controller, although clock on pll_ref_clk input is present?

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You can get any interface out of a Platform Designer system by adding in a bridge component and exporting the extra interface. You'd use a clock bridge component for this, but since you are using the hardened interface, I don't know if it's possible to connect that back to soft FPGA logic.

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Thanks for the information, I'll keep that in mind for future Qsys usage.

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Hi, If you trace the RTL, you can see the afi_clk is direct connect from the PLL out_clk port.

So, the only reason why no clock is due to PLL is lose lock.

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That piece of advice was very helpful, thank you. On RTL view I noticed that PLL's reset is inverse. There's a standart inverse symbol on PLL reset pin.

I guess, on top level schematic view leter "n" at the end of megafunction reset pin name ( global_reset_n) stands for "negative" and means the same.

That was a bit unexpected :-)

Turns out, I 've keeping the controller in reset all the time, no wonder everything seemed dead.

So far so good, the afi_clk is running now :-)