Altera_Forum
Honored Contributor
Honored ContributorWhy PCIe signals tx_st and rx_st are different for CIV and CV in QSys?
Why does "Cyclone V Hard IP for PCI Express" have tx_st and rx_st as Avalon-ST sink and Avalon-ST source in QSys, but "IP Compiler for PCI Express" for Cyclone IV have it only as Conduits?
