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Altera_Forum's avatar
Altera_Forum
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12 years ago

Why don't we simulate the synthesis code ?

Hello, I have a long standing methodological question about the IP generation tools from Altera. They seem to all generate 2 sets of VHDL/Verilog code: one for synthesis, one for simulation. ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

No, I am not speaking about synthesis at all, just IP generation.

Let me point you to a clear example, if you generate any AvalonMM interconnect, in the "synthesis/submodules" subfolder you will find a file called "altera_avalon_mm_bridge.v". This file can be found (or the template of it more precisely) under <your_quartus_path>\ip\altera\merlin\altera_avalon_mm_bridge. It is a perfectly good file for simulation.

So, what does the "simulation" folder bring to the party ?