Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorWhy don't we simulate the synthesis code ?
Hello, I have a long standing methodological question about the IP generation tools from Altera. They seem to all generate 2 sets of VHDL/Verilog code: one for synthesis, one for simulation. ...
Altera_ForumHonored Contributor
Honored Contributorthe simulation folder probbly cpntains simulation models, with synthesis containing netlists ( not simulatable directly). you could simulate a post place a route model, if you've got lots of spare time.
