Why does Fitter show "Dedicated Pin" as "Reference Clock Source by" for downstream PLL in cascade?

Hi everyone,

I created a design that connects two PLLs in a simple cascaded configuration.

However, I noticed something that seems inconsistent in the Fitter report:

•  In the Resource Section → PLL Usage Summary, the "Reference Clock Sourced by" field for the downstream side PLL shows "Dedicated Pin". This seems unusual because it does not reflect the actual connection (which uses the upstream side PLL’s cascade output).
• On the other hand, the "PLL Refclk Select" section in the report looks correct and matches the intended cascading setup.

Could anyone explain why this discrepancy occurs?

Is this normal behavior or a reporting issue in Quartus Prime?

Environment:

• Tool: Quartus Prime Standard Edition version 23.11
• Target Device: Cyclone V GX (5CGXFC5F6M11C6)
• Target IP: "Altera PLL" or "PLL Intel FPGA"

Sample Design:

• Simple_Two_plls_shortest_cascading_refclk_from_clkpin.qar

Settings Summary (Only the key parameters are listed.):

Upstream side PLL:

In [General] tab

• PLL Mode: Integer-N PLL
• Operation Mode: Normal
• Feedback Clock: Global Clock

In [Cascading] tab

• "Create a 'cascade_out' signal to connect with a downstream PLL" : Enabled

           ( PLL Use As Upstream PLL. → Create cascade_out signal )

In [Settings] tab

• Bandwidth Preset: Low

Downstream side PLL:

In [General] tab

• PLL Mode: Integer-N PLL
• Operation Mode: Normal
• Feedback Clock: Global Clock

In [Cascading] tab

• "Create an adjpｌｌin or cclk signal to connect with an upstream PLL" : Enabled

         ( PLL Use As Downstream PLL → Create adjpll_in or cclk signal )

In [Settings] tab

• Bandwidth Preset: High

Thank you for any insights on this!