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MJost3's avatar
MJost3
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6 years ago

Why do I see incorrect functionality in hardware when using the dcfifo IP in a Cyclone IV E FPGA design?

In my design targeting a Cyclone IV E FPGA I use several dcfifo FIFOs. I observed that the first write/read FIFO transaction (after the FPGA is configured) sometimes fails in hardware. In such an err...
MJost3's avatar
MJost3
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6 years ago

Hi Shyan ,

  • The test was performed at room temperature.
  • It is always the first transaction that fails. I rebooted the FPGA using an automated script and approx. at every 100th reboot the first transaction fails.
  • I could not reproduce this error if I reset the FIFOs at start-up using the aclr port. However, the datasheet claims that using the aclr port is optional.
  • The design successfully compiled without any timing violations (I did not specifiy specific timing constraints for these FIFOs since they are provided by Altera. Is this correct?

Thanks for looking at it,

Best, Michael